/**
 * Async read, sync write memory.
 **/
module Memory(raddr, waddr, clk, wen, in, out, reset);
   //pin declarations
   input wire [31:0] raddr, waddr;
   input wire        wen, clk;
   input wire [31:0] in;
   output wire [31:0] out;
   input wire         reset;

   //memory declarations
   reg [31:0]         mem[0:256];
   integer            i;

   //write logic
   always@(posedge clk or posedge reset) begin
      if (reset) begin
         mem[0] <= 2;
         mem[1] <= 4;
         mem[2] <= 95;
         mem[3] <= 13;

         mem[4] <= 19;
         mem[5] <= 53;
         mem[6] <= 23;
         mem[7] <= 59;

         mem[8] <= 199;
         mem[9] <= 253;
         mem[10] <= 79;
         mem[11] <= 58;

         mem[12] <= 69;
         mem[13] <= 190;
         mem[14] <= 85;
         mem[15] <= 79;
      end
      else if (wen) begin
         mem[waddr[7:0]] <= in;
      end
   end

   assign out = mem[raddr[7:0]];

endmodule
